? semiconductor components industries, llc, 2009 may, 2009 ? rev. 0 1 publication order number: cat5172/d cat5172 256-position spi compatible digital potentiometer the cat5172 is a 256 ? position digitally programmable linear taper potentiometer ideally suited for replacing mechanical potentiometers and variable resistors. like mechanical potentiometers, the cat5172 has a resistive element, which can span v cc to ground or float anywhere between the power supply rails. wiper settings are controlled through an spi ? compatible digital interface. upon power ? up, the wiper assumes a mid ? span position and may be repositioned anytime after the power is stable. the cat5172 operates from 2.7 v to 5.5 v, while consuming less than 2 a. this low operating current, combined with a small package footprint, make the cat5172 ideal for battery ? powered portable appliance. features ? 256 ? position ? end ? to ? end resistance: 50 k , 100 k ? spi compatible interface ? power ? on preset to midscale ? single supply 2.7 v to 5.5 v ? low temperature coefficient 100 ppm/ c ? low power, i dd 2 a max ? wide operating temperature ? 40 c to +85 c ? rohs ? compliant sot ? 23 8 ? lead (2.9 mm x 3 mm) package ? this is a pb ? free device typical applications ? potentiometer replacement ? transducer adjustment of pressure, temperature, position, chemical, and optical sensors ? rf amplifier biasing ? gain control and offset adjustment http://onsemi.com pin connections sdi cs b a clk gnd v dd w 1 (top view) see detailed ordering and shipping information in the package dimensions sect ion on page 2 of this data sheet. ordering information sot23 ? 8 tb suffix case 527ak ad = 50 k ae = 100 k y = production year y = (last digit) m = production month m = (1 ? 9, a, b, c) adym marking diagram 1 aeym 1
cat5172 http://onsemi.com 2 spi interface wiper register clk a b w sdi gnd figure 1. functional block diagram v dd cs table 1. ordering information part number resistance temperature range package shipping ? cat5172tbi ? 50gt3 50 k ? 40 c to 85 c sot ? 23 ? 8 (pb ? free) 3000/tape & reel cat5172tbi ? 00gt3 100 k 3000/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. table 2. pin function description pin no. pin name description 1 w resistor?s wiper terminal. 2 v dd positive power supply. 3 gnd digital ground. 4 clk serial clock input. positive edge triggered. 5 sdi serial data input. 6 cs chip select input, active low. when cs returns high, data will be loaded into the dac register. 7 b bottom terminal of resistive element. 8 a top terminal of resistive element. table 3. absolute maximum ratings (note 1) rating value unit v dd to gnd ? 0.3 to 6.5 v v a , v b , v w to gnd v dd i max 20 ma digital inputs and output voltage to gnd 0 to 6.5 v operating temperature range ? 40 to +85 c maximum junction temperature (t jmax ) 150 c storage temperature ? 65 to +150 c lead temperature (soldering, 10 sec) 300 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package , and maximum applied voltage across any two of the a, b, and w terminals at a given resistance.
cat5172 http://onsemi.com 3 table 4. electrical characteristics: 50 k and 100 k versions v dd = 5 v 10%, or 3 v 10%; v a = v dd ; v b = 0 v; ?40 c < t a < +85 c; unless otherwise noted. parameter test conditions symbol min typ (note 2) max unit dc characteristics ? rheostat mode resistor differential nonlinearity (note 3) r wb , v a = no connection r ? dnl ? 1 0.1 +1 lsb resistor integral nonlinearity (note 3) r wb , v a = no connection r ? inl ? 2 0.4 +2 lsb nominal resistor tolerance (note 4) t a = 25 c r ab ? 20 +20 % resistance temperature coefficient v ab = v dd , wiper = no connection r ab / t 100 ppm/ c wiper resistance v dd = 5 v r w 50 120 v dd = 3 v 100 250 dc characteristics ? potentiometer divider mode resolution n 8 bits differential nonlinearity (note 5) dnl ? 1 0.1 +1 lsb integral nonlinearity (note 5) inl ? 1 0.4 +1 lsb voltage divider temperature coefficient code = 0x80 v w / t 100 ppm/ c full ? scale error code = 0xff v wfse ? 3 ? 1 0 lsb zero ? scale error code = 0x00 v wzse 0 1 3 lsb resistor terminals voltage range (note 6) v a,b,w gnd v dd v capacitance (note 7) a, b f = 1 mhz, measured to gnd, code = 0 x 80 c a,b 45 pf capacitance (note 7) w f = 1 mhz, measured to gnd, code = 0 x 80 c w 60 pf common ? mode leakage (note 7) v a = v b = v dd /2 i cm 1 na digital inputs input logic high v dd = 5 v v ih 0.7 x v dd v input logic low v dd = 5 v v il 0.3v dd v input logic high v dd = 3 v v ih 0.7 x v dd v input logic low v dd = 3 v v il 0.3v dd v input current v in = 0 v or 5 v i il 1 a input capacitance (note 7) c il 5 pf power supplies power supply range v dd range 2.7 5.5 v supply current v ih = 5 v or v il = 0 v i dd 0.3 2 a power dissipation (note 8) v ih = 5 v or v il = 0 v, v dd = 5 v p diss 0.2 mw power supply sensitivity v dd = +5 v 10%, code = midscale pss 0.05 %/% 2. typical specifications represent average readings at +25 c and v dd = 5 v. 3. resistor position nonlinearity error r ? inl is the deviation from an ideal value measured between the maximum resistance and the minim- um resistance wiper positions. r ? dnl measures the relative step change from ideal between successive tap positions. parts are guaran- teed monotonic. 4. v ab = v dd , wiper (v w ) = no connect. 5. inl and dnl are measured at vw with the dpp configured as a potentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 6. resistor terminals a, b, w have no limitations on polarity with respect to each other. 7. guaranteed by design and not subject to production test. 8. pdiss is calculated from (i dd x v dd ). cmos logic level inputs result in minimum power dissipation. 9. all dynamic characteristics use v dd = 5 v.
cat5172 http://onsemi.com 4 table 4. electrical characteristics: 50 k and 100 k versions (continued) v dd = 5 v 10%, or 3 v 10%; v a = v dd ; v b = 0 v; ?40 c < t a < +85 c; unless otherwise noted. parameter unit max typ (note 2) min symbol test conditions dynamic characteristics (notes 7 and 9) bandwidth ?3 db r ab = 50 k / 100 k , code = 0x80 bw 100/40 khz total harmonic distortion v a =1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k thd w 0.05 % v w settling time (50 k /100 k ) v a = 5 v, v b = 0 v, 1 lsb error band t s 2 s 2. typical specifications represent average readings at +25 c and v dd = 5 v. 3. resistor position nonlinearity error r ? inl is the deviation from an ideal value measured between the maximum resistance and the minim- um resistance wiper positions. r ? dnl measures the relative step change from ideal between successive tap positions. parts are guaran- teed monotonic. 4. v ab = v dd , wiper (v w ) = no connect. 5. inl and dnl are measured at vw with the dpp configured as a potentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 6. resistor terminals a, b, w have no limitations on polarity with respect to each other. 7. guaranteed by design and not subject to production test. 8. pdiss is calculated from (i dd x v dd ). cmos logic level inputs result in minimum power dissipation. 9. all dynamic characteristics use v dd = 5 v. table 5. timing characteristics: 50 k and 100 k versions v dd = 5 v 10%, or 3 v 10%; v a = v dd ; v b = 0 v; ?40 c < t a < +85 c; unless otherwise noted. parameter test conditions symbol min typ (note 10) max unit spi interface timing characteristics (notes 11 and 12) (specifications apply to all parts) clock frequency f clk 25 mhz input clock pulse width clock level high or low t ch , t cl 20 ns data setup time t ds 5 ns data hold time t dh 5 ns cs setup time t css 15 ns cs high pulse width t csw 40 ns clk fall to cs fall hold time t csh0 0 ns clk fall to cs rise hold time t csh1 0 ns cs rise to clock rise setup t cs1 10 ns 10. typical specifications represent average readings at +25 c and v dd = 5 v. 11. guaranteed by design and not subject to production test. 12. see timing diagram for location of measured values. all input control voltages are specified with t r = t f = 2 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v.
cat5172 http://onsemi.com 5 spi interface table 6. ca t5172 serial data ? word format b7 b6 b5 b4 b3 b2 b1 b0 d7 msb 2 7 d6 d5 d4 d3 d2 d1 d0 lsb 2 0 figure 2. cat5172 spi interface timing diagram (v a = 5 v, v b = 0 v, v w = v out ) data in cs clk sdi v1 v2 v out 1 234 5 678 d7 d6 d5 d4 d3 d2 d1 d0 sdi clk vout 1 0 1 0 1 0 (data in) dx dx figure 3. spi interface detailed timing diagram (v a = 5 v, v b = 0 v, v w = v out ) v w0 v w t s 1 lsb t csw cs t cs1 t css t csho t ds t dh t ch t cl t csh1
cat5172 http://onsemi.com 6 typical characteristics v cc = 2.6 v 3.3 v 5.6 v 4.0 v figure 4. differential non ? linearity, v cc = 5.6 v figure 5. integral non ? linearity, v cc = 5.6 v tap tap 256 224 160 128 96 64 32 0 ? 0.05 ? 0.04 ? 0.03 ? 0.02 ? 0.01 0.01 0.02 0.03 224 192 160 128 96 64 32 0 ? 0.5 ? 0.4 ? 0.3 ? 0.2 ? 0.1 0 0.1 figure 6. wiper resistance at room temperature figure 7. wiper voltage tap tap 250 200 150 100 50 0 0 20 40 60 80 100 120 260 208 156 104 52 0 0 1 2 3 4 5 6 figure 8. change in end ? to ? end resistance figure 9. end ? to ? end resistance vs. temperature temperature ( c) temperature ( c) 100 70 40 10 ? 20 ? 50 ? 0.2 0 0.2 0.4 100 70 40 10 ? 20 ? 50 101.75 101.80 101.85 101.90 101.95 102.00 102.05 102.15 error (lsb) error (lsb) rw ( ) vw (v) (%) r (k ) 0 192 dnl inl 256 v cc = 2.6 v 3.3 v 5.6 v 4.0 v 5.0 v 102.10
cat5172 http://onsemi.com 7 typical characteristics figure 10. wiper?s transition from position 0xff to position 0x00 relative to the cs disable, v cc = 5 v figure 11. standby current v cc (v) w cs 6 5 4 3 2 100 150 200 250 300 350 400 figure 12. gain vs. bandwidth (tap 0x80) figure 13. psrr f (khz) f (khz) 1000 100 10 1 ? 36 ? 30 ? 24 ? 18 ? 12 ? 6 0 1000 100 10 1 0 5 10 15 20 25 30 isb (na) a (db) psrr (db) t = ? 45 c t = 25 c t = 90 c v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v
cat5172 http://onsemi.com 8 basic operation the cat5172 is a 256 ? position digitally controlled potentiometer. when power is first applied the wiper assumes a mid ? scale position and will remain there as long as cs remians high. once the power supply is stable the wiper may be repositioned via the spi compatible interface. the rising edge of the cs signal acts as the transfer command and each time cs transitions from low to high the contents of the input register are loaded into the wiper register. in the power ? up cycle, the input data register is cleared, setting all bits to 0 and the wiper register is loaded with 0x80 (128 decimal) which moves the wiper to its midscale position. if cs is toggled cat5172 transfers the contents of the input data register (0x00) to the wiper register moving the wiper to the bottom ? most position (w = terminal b). this transfer is independent of whether new data has been input or not because cs acts as the transfer command. programming: variable resistor rheostat mode the resistance between terminals a and b, r ab , has a nominal value of 50 k or 100 k and has 256 contact points accessed by the wiper terminal, plus the b terminal contact. data in the 8 ? bit w iper register is decoded to select one of these 256 possible settings. the wiper?s first connection is at the b terminal, corresponding to control position 0x00. ideally this would present a 0 between the wiper and b, but just as with a mechanical rheostat there is a small amount of contact resistance to be considered, there is a wiper resistance comprised of the r on of the fet switch connecting the wiper output with its respective contact point. in cat5172 this ?contact? resistance is typically 50 . thus a connection setting of 0x00 yields a minimum resistance of 50 between terminals w and b. for a 100 k device, the second connection, or the first tap point, corresponds to 441 (r wb = r ab /256 + r w = 390.6 + 50 ) for data 0x01. the third connection is the next tap point, is 831 (2 x 390.6 + 50 ) for data 0x02, and so on. figure 14 shows a simplified equivalent circuit where the last resistor string will not be accessed; therefore, there is 1 lsb less of the nominal resistance at full scale in addition to the wiper resistance. figure 14. cat5172 equivalent dpp circuit r s wiper register and decoder a w b r s r s r s the equation for determining the digitally programmed output resistance between w and b is r wb d 256 r ab r w (eq. 1) where d is the decimal equivalent of the binary code loaded in the 8 ? bit wiper register, r ab is the end ? to ? end resistance, and r w is the wiper resistance contributed by the on resistance of the internal switch. in summary, if r ab = 100 k and the a terminal is open circuited, the following output resistance r wb will be set for the indicated wiper register codes: table 7. codes and corresponding r wb resistance for r ab = 100 k , v dd = 5 v d (dec.) r wb ( ) output state 255 99,559 full scale (r ab ? 1 lsb + r w ) 128 50,050 midscale 1 441 1 lsb 0 50 zero scale (wiper contact resistance) be aware that in the zero ? scale position, the wiper resistance of 50 is still present. current flow between w and b in this condition should be limited to a maximum pulsed current of no more than 20 ma. failure to heed this restriction can cause degradation or possible destruction of the internal switch contact. similar to the mechanical potentiometer, the resistance of the dpp (digitally programmed potentiometer) between the wiper w and terminal a also produces a digitally controlled complementary resistance r wa . when these terminals are used, the b terminal can be opened. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. the general equation for this operation is r wa (d) 256 d 256 r ab r w (eq. 2)
cat5172 http://onsemi.com 9 for r ab = 100 k and the b terminal open circuited, the following output resistance r wa will be set for the indicated wiper register codes. table 8. codes and corresponding r wa resistance for r ab = 100 k , v dd = 5 v d (dec.) r wa ( ) output state 255 441 full scale 128 50,050 midscale 1 99,659 1 lsb 0 100,050 zero scale typical device to device resistance matching is lot dependent and may vary by up to 20%. spi compatible 3 ? wire serial bus control of cat5172 is through a 3 ? wire spi compatible digital interface (sdi, cs , and clk). the clk input is rising ? edge sensitive and requires crisp transitions to avoid clocking incorrect data into the serial input register. when cs is low, the clock loads data into the serial register on each positive clock edge (figure 1). each 8 ? bit serial word must be loaded starting with the msb. the format of the word is shown in table 6. data loaded into cat5172?s 8 ? bit serial input register is transferred to the internal wiper register when the cs line returns to logic high. extra msb bits are ignored. esd protection gnd logic digital input gnd potentiometer figure 15. esd protection networks terminal voltage operating range the cat5172 v dd and gnd power supply define the limits for proper 3 ? terminal digital potentiometer operation. signals or potentials applied to terminals a, b or the wiper must remain inside the span of v dd and gnd. signals which attempt to go outside these boundaries will be clamped by the internal forward biased diodes. w, a, b cat5172 logic gnd figure 16. v dd power ? up sequence because esd protection diodes limit the voltage compliance at terminals a, b, and w (see figure 15), it is recommended that v dd /gnd be powered before applying any voltage to terminals a, b, and w. the ideal power ? up sequence is: gnd, v dd , digital inputs, and then v a/b/w . the order of powering v a , v b , v w , and the digital inputs is not important as long as they are powered after v dd /gnd. power supply bypassing good design practice employs compact, minimum lead length layout design. leads should be as direct as possible. it is also recommended to bypass the power supplies with quality low esr ceramic chip capacitors of 0.01 f to 0.1 f. low esr 1 f to 10 f tantalum or electrolytic capacitors can also be applied at the supplies to suppress transient disturbances and low frequency ripple. as a further precaution digital ground should be joined remotely to the analog grou nd at one point to minimize the ground bounce. cat5172 gnd + 10 f 0.1 f figure 17. power supply bypassing v dd v dd c 3 c 1
cat5172 http://onsemi.com 10 package dimensions sot ? 23, 8 lead case 527ak ? 01 issue a notes: (1) all dimensions in millimeters. angles in degrees. (2) complies with jedec standard mo-178. symbol e e1 a2 a3 a1 eb d c a top view side view end view l1 l2 l pin #1 identification min nom max a a1 a2 b c d e e1 l l2 0.00 0.90 0.28 0.08 2.90 bsc 1.60 bsc 0.45 1.45 0.15 1.30 0.38 0.22 0.25 ref 1.10 2.80 bsc l1 0.60 ref e 0.30 0.60 0.65 bsc 0.90 0 8 a3 0.60 0.80 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. cat5172/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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